Marvell Technology (MRVL): Building the Data Movement Infrastructure of AI Data Centers

September 1, 2026

AI Civilization Map Node: Marvell AI Data Movement Infrastructure
Primary Map Layer: Semiconductors, Compute & Packaging — Machine Substrate
Primary Map Branch: Packaging & Optical Interconnects
Secondary Map Layer: Fiber, Networks & Distributed Intelligence — Coordination Fabric
Supporting Map Layer: Geopolitics, Sovereignty & Constraints — Boundary Conditions
Structural Function: Connects custom compute, memory, switching, and optical interfaces into scalable AI data-movement paths across racks, clusters, and data-center domains.
Matrix Category: AI Hardware
Stock Price: $200.88 (Recorded at publication as a structural reference point. Future price reflects whether the industrial thesis held.)

Overview

For most of the first phase of the generative-AI infrastructure buildout, the industry asked a relatively simple question: how can more computation be brought online? The resulting bottlenecks were visible and easy to name. GPUs were scarce. High-bandwidth memory was scarce. Advanced packaging capacity was scarce. Power and data-center space were scarce. The market therefore learned to think about AI infrastructure mainly through the lens of processors, accelerator supply and electricity.

That view is becoming incomplete. As AI systems scale from individual accelerators to racks, pods, clusters and multiple data centers, the performance of the system increasingly depends on how quickly and efficiently data can move between computation, memory, storage and networks. A processor that cannot access memory fast enough stalls; host CPUs can become a separate coordination bottleneck as well, a problem examined in Why CPU Is Becoming the Bottleneck in AI Infrastructure. A rack that cannot exchange data with neighboring racks wastes expensive compute. A cluster that repeatedly converts, retimes or transports signals across inefficient links loses power to communication instead of useful model work. As these systems scale, AI infrastructure becomes not only a compute problem but also a data movement problem. This broader physical transition is explored in The Fiber Limit of AI Civilization, which maps how data movement expands from boards and racks into campuses and regions.

Marvell Technology is structurally relevant because its portfolio increasingly spans many of the physical paths along which that data moves. Its custom-silicon business places the company close to hyperscaler accelerator architectures. Its networking and interface products connect processors to the systems around them. Its Compute Express Link (CXL) products address memory expansion and pooling. Its Inphi-derived electro-optics portfolio processes high-speed optical traffic. Its acquisition of XConn adds PCIe and CXL switching and strengthens its UALink scale-up roadmap. Its acquisition of Celestial AI extends the portfolio toward optical scale-up through Photonic Fabric. In 2026, strategic relationships with NVIDIA and Google further widened the number of AI architectures into which Marvell may be embedded.

The breadth matters because AI communication is not one homogeneous market. A signal traveling a few centimeters across a package encounters different constraints from data moving across a board, a rack, a row, a building or a 1,000-kilometer optical route. The protocol, electrical budget, latency tolerance, modulation method, packaging technology and economics all change with distance. Marvell's portfolio is more usefully read as a set of technologies positioned at different distance and resource boundaries inside the same AI machine rather than as a list of unrelated product families.

That interpretation also helps explain why the company has continued to buy businesses after already possessing custom silicon and optical products. The 2021 Inphi acquisition brought electro-optics and coherent data-center interconnect. The 2026 XConn acquisition added high-radix PCIe and CXL switching for electrical scale-up. Celestial AI added an optical scale-up architecture. These transactions move progressively deeper into the problem of connecting larger numbers of compute and memory resources while limiting communication power, reach and latency penalties.

This article therefore does not treat Marvell primarily as a second-source custom ASIC vendor. Custom compute is important, but it is only one entry point into a broader architectural position. The more consequential question is whether Marvell can become one of the semiconductor companies that sits across the paths connecting compute, memory, storage, racks and data centers.

Structural anchor and temporal scope. This Matrix assessment uses a 5–15-year structural horizon. Its core constraint is that as accelerator counts and model-state footprints scale, useful AI throughput increasingly depends on moving data among compute, memory, storage and network resources within acceptable latency and energy-per-bit budgets; changing the processor architecture does not remove that requirement. The evidence base is deliberately multi-vector: U.S. securities filings and disclosed commercial agreements, Taiwan-based advanced-foundry dependence through TSMC, and physical engineering constraints in bandwidth, signal integrity, distance and power.

Key Takeaways

• Marvell is already predominantly a data-center company: Q2 FY2027 data-center revenue reached approximately $2.17 billion, or 79% of total revenue, with 46% year-over-year growth. See the financial reality check.
• The Google relationship is broader than one custom ASIC: the disclosed programs span inference accelerators, NICs, memory-interface controllers, storage controllers and near-memory compute around the TPU ecosystem. The associated warrant is performance-based; Google does not simply own 7% of Marvell today. See the warrant structure.
• Marvell's current position was assembled over years: Cavium expanded infrastructure compute, Avera added custom-ASIC depth, Inphi added electro-optics, Innovium added cloud switching, XConn added electrical scale-up and Celestial AI extended the roadmap toward optical scale-up. See the capability timeline.
• The structural thesis is broader than the compute winner: GPUs, TPUs, Trainium and Maia can compete while all still generate demand for memory, switching, SerDes, DSPs and optical links. Marvell's opportunity is to occupy valuable interfaces across those architectures.
• The thesis still carries substantial execution risk: hyperscaler concentration, custom-silicon margin mix, standards uncertainty and the commercialization of Photonic Fabric can all limit how much of the addressable infrastructure Marvell ultimately captures. See risks and counterarguments.

AI Infrastructure Is Moving from a Compute Scarcity Problem to a Data Movement Problem

The first bottleneck was obvious: more compute

The early AI infrastructure cycle was dominated by the scarcity of accelerators and the physical resources required to deploy them. Large cloud providers and AI laboratories competed for GPUs, HBM, advanced-node wafers, CoWoS-class packaging, power allocations and new data-center capacity. Under those conditions, the processor naturally became the center of the infrastructure narrative. The upstream scarcity of HBM, advanced packaging and manufacturing equipment is examined separately in AI’s Next Bottleneck: The Coming Semiconductor Equipment Supercycle.

That framing remains valid, but it becomes less sufficient as the number of accelerators rises. A useful way to see the transition is to move outward from one XPU. A single accelerator needs memory bandwidth. Multiple accelerators need low-latency communication. A rack needs switches, retimers, NICs and optical links. Multiple racks require scale-up and scale-out fabrics. Large sites require optical transport across buildings and campuses. Distributed sites require data-center interconnect. Every layer adds additional movement of data.

A topology vocabulary: scale-up, scale-out and scale-across

The industry's language can be confusing because several connectivity domains overlap physically while serving different system functions. Scale-up generally refers to tightly coupling accelerators and memory resources so that they behave more like one larger computing system. The priorities are very high bandwidth, deterministic or extremely low latency, cache or memory semantics where applicable, and the ability to keep accelerators synchronized. Technologies in this domain include proprietary links such as NVLink as well as emerging open approaches such as UALink, plus PCIe and CXL for particular device and memory functions.

Scale-out connects servers, racks and accelerator islands through a network. Ethernet is becoming increasingly important here because hyperscalers want open, multi-vendor fabrics that can expand across large clusters. Scale-out can tolerate more network behavior than the tightest scale-up domains, but AI workloads still punish congestion, packet loss and tail latency because thousands of expensive accelerators may be waiting on collective operations.

A third domain can be described as scale-across: moving data between buildings, campuses, metro sites and regional data centers. This is where coherent optical transport, ZR/ZR+ pluggables and data-center interconnect become relevant. In a distributed AI system, these domains are not independent. The output of one layer becomes the traffic input of the next. The practical architecture therefore resembles a hierarchy of fabrics rather than a single network. For a system-level treatment of this outer layer, see AI Scale-Across Infrastructure.

This vocabulary is important for understanding Marvell. XConn primarily strengthens electrical scale-up and memory fabrics. Teralynx and high-speed Ethernet interfaces address scale-out. Inphi-derived PAM4 DSPs enable short- and medium-reach optical scale-out. Coherent DSPs and COLORZ products address scale-across. Celestial AI attempts to push optics inward into the scale-up domain itself. The company is effectively trying to occupy multiple rungs of the connectivity hierarchy rather than dominate one protocol.

Connectivity domain	Primary system function	Representative standards / technologies	Representative Marvell position
Scale-up	Tightly couple accelerators and memory with very low latency	UALink, NVLink-compatible interfaces, PCIe	XConn switching, retimers, custom silicon, NVLink Fusion-compatible scale-up networking
Memory fabric	Expand, pool and expose memory resources beyond one local socket	CXL over PCIe physical infrastructure	Structera memory expansion, near-memory acceleration and CXL switching
Scale-out	Connect servers, racks and accelerator islands across a cluster	Ethernet, UEC-oriented fabrics, PAM4 optics	Teralynx switching, high-speed SerDes, PAM4 DSPs and 800G/1.6T optical interconnect
Scale-across	Move data between buildings, campuses and regional data centers	Coherent optics, 800G ZR/ZR+	Coherent DSPs and COLORZ pluggable optics
Emerging optical scale-up	Extend scale-up reach and bandwidth across larger multi-rack domains	Optical I/O / photonic fabric architectures	Celestial AI Photonic Fabric

The categories overlap because protocols can share physical layers and products can serve more than one topology. The table is therefore a system map rather than a rigid taxonomy. Its purpose is to show why the terms PCIe, CXL, UALink, Ethernet, PAM4 and coherent optics cannot be treated as interchangeable: they solve different parts of the same data-movement hierarchy.

The system can only be as fast as its slowest data path

AI workloads are unusually sensitive to communication bottlenecks because expensive compute resources are valuable only while they are doing useful work. If an accelerator is waiting for parameters, key-value cache, training gradients, storage data or another accelerator, the system is paying for silicon and power while receiving less useful throughput. This is why memory bandwidth, interconnect latency, link utilization and network congestion increasingly influence tokens per dollar and performance per watt.

The issue is especially important as systems move toward larger scale-up domains and more distributed inference. Training requires large groups of accelerators to exchange data repeatedly. Inference increasingly requires access to large model states, long-context caches and external memory. Agentic systems can intensify this pressure because many concurrent tasks may require persistent state and repeated movement between compute and memory resources.

The architectural implication is simple: adding more accelerators can create more than proportional demand for the infrastructure surrounding them. One additional XPU can require additional NIC capacity, switch ports, SerDes lanes, retimers, memory interfaces and optical links. The addressable system is therefore larger than the processor socket alone.

The economics become more severe as accelerators become more expensive. If a cluster worth billions of dollars operates even a few percentage points below its potential because communication or memory stalls are poorly managed, the lost output can be economically larger than the cost of many connectivity components that prevent those stalls. This gives hyperscalers an incentive to optimize not only raw link speed but effective utilization per watt and per dollar of installed compute.

Data movement also consumes power twice: once directly in PHYs, retimers, switches, DSPs and optical modules, and again indirectly when underfed accelerators wait without producing useful tokens or training progress. This is why the industry is pushing optical conversion closer to the source of traffic, experimenting with memory pooling, and designing custom NICs and controllers around specific accelerator architectures. The goal is not merely to move more bits. It is to move the right bits with less energy and less idle time.

Marvell's opportunity sits in the paths between resources

Marvell's portfolio can be read as a map of those paths. Custom silicon can place Marvell inside the compute architecture. CXL and PCIe products connect compute with memory and peripherals. Ethernet and scale-up switching move traffic within racks and pods. PAM4 DSPs and related electro-optics move traffic into optical fiber. Coherent optics move traffic across longer data-center distances. Photonic Fabric is intended to push optics deeper into scale-up domains.

This does not mean Marvell controls every layer, nor that one vendor necessarily owns the entire interconnect stack. It means the company has become exposed to several different forms of the same structural requirement: AI systems are moving increasing volumes of data across more distances, with rising pressure on latency and energy per bit.

The Corporate Transformation: From Traditional Semiconductor Portfolio to Data Infrastructure

Marvell's older businesses already revolved around moving and storing data

Marvell did not begin as an AI company. Its historical portfolio included storage controllers, networking silicon, communications products and consumer-oriented semiconductors. Yet an important continuity runs through much of that history: the company repeatedly worked on technologies that move, store, process or secure data rather than focusing exclusively on general-purpose compute.

Under CEO Matt Murphy, that orientation became a deliberate infrastructure strategy. Marvell's 2026 proxy statement describes a decade-long reshaping in which the company completed more than $24 billion of acquisitions and nearly $4.5 billion of divestitures, while progressively concentrating the portfolio around high-speed interconnects, custom silicon, switching and storage. The direction matters more than the aggregate transaction value: Marvell repeatedly bought engineering capabilities that sit at different boundaries in data infrastructure and sold businesses that were less central to that architecture.

The capability-acquisition timeline explains today's portfolio better than any single deal

Year	Capability added	Why it matters to today's AI data-movement stack
2018	Cavium — infrastructure compute, networking and security	Expanded Marvell beyond storage into a broader infrastructure platform and added complex SoC and processing capabilities.
2019	Avera Semiconductor — custom ASIC design	Added deep IBM-microelectronics heritage, full-custom development capability, high-speed SerDes, embedded memory and advanced-packaging expertise that became foundational to Marvell's custom-silicon position.
2021	Inphi — high-speed electro-optics and coherent interconnect	Added PAM4 and coherent DSP depth and moved Marvell directly into the optical paths that became increasingly critical as AI clusters scaled.
2021	Innovium — cloud-optimized Ethernet switching	Added the Teralynx switch family and strengthened Marvell's position in cloud data-center scale-out networking.
2026	Celestial AI — Photonic Fabric	Extended the roadmap toward optical scale-up and optical shared-memory architectures across larger multi-rack domains.
2026	XConn Technologies — PCIe and CXL switching	Deepened electrical scale-up and memory-fabric capability while strengthening engineering resources for UALink switching.

Seen in sequence, the acquisitions are not a random collection of semiconductor businesses. Cavium broadened infrastructure compute; Avera supplied the custom-ASIC execution layer; Inphi supplied optical signal processing; Innovium added cloud switching; XConn moved deeper into electrical scale-up and memory fabric; Celestial AI pushed optics inward toward the scale-up domain. The portfolio that appears broad in 2026 is the accumulated result of these capability additions.

Avera is the missing link in the custom-silicon story

The 2019 acquisition of Avera Semiconductor deserves particular attention because it explains why Marvell's custom-silicon position cannot be reduced to a recent AI design-services push. Avera was the ASIC business of GLOBALFOUNDRIES and originated in IBM Microelectronics. At the time of the acquisition, Marvell described the team as having roughly 25 years of custom-design heritage, with expertise spanning analog and mixed-signal design, high-speed SerDes, embedded memory and advanced packaging. That institutional knowledge became part of the technical base from which Marvell could pursue increasingly complex cloud and AI custom silicon.

This history also clarifies the relationship between custom compute and connectivity inside Marvell. The same custom program that needs physical design and packaging also needs proven interface IP, SerDes, memory controllers and networking. Avera did not make optics or cloud switching redundant; it created a custom implementation layer that could increasingly draw on capabilities added elsewhere in the portfolio.

Inphi and Innovium moved Marvell from custom infrastructure toward optical and cloud fabrics

The 2021 acquisition of Inphi was one of the most consequential moves in Marvell's transformation. Inphi brought high-speed data movement technology based on optical interconnects, including PAM DSPs, coherent DSPs, laser drivers, transimpedance amplifiers, optical PHY technology and silicon-photonics capabilities. Marvell's fiscal filings placed total merger consideration at approximately $9.92 billion. This was not a small technology tuck-in; it materially reweighted the company toward cloud networking and electro-optics before generative AI made optical bandwidth a mainstream infrastructure constraint.

Later in 2021, Innovium added cloud-optimized Ethernet switching through the Teralynx family. That deal matters because a data-movement strategy needs more than optical endpoints. Large AI systems require switches that aggregate and direct traffic across the cluster. Inphi and Innovium therefore strengthened two adjacent parts of the same scale-out problem: moving high-speed signals over fiber and switching the resulting traffic through cloud fabrics.

Portfolio pruning was part of the same strategy

Marvell's transformation was not only acquisitive. The company divested businesses including Wi-Fi connectivity and, in August 2025, automotive Ethernet. Its current reporting structure groups revenue primarily into Data Center and Communications and Other. The result is a much more concentrated corporate identity than the legacy portfolio implied: engineering and capital are increasingly directed toward cloud, AI, networking, storage and high-speed data infrastructure.

This makes the 2026 acquisitions easier to interpret. XConn adds PCIe and CXL switching at a time when memory disaggregation and accelerator scale-up are becoming more important. Celestial AI adds optical interconnect technology aimed at larger scale-up domains as electrical reach, bandwidth and power become harder constraints. These transactions do not prove commercial success, but they continue the same capability-building pattern visible in Avera, Inphi and Innovium.

Custom Silicon Is an Entry Point, Not the Whole Marvell Story

Why hyperscalers build custom XPUs

Custom accelerators allow large cloud providers to optimize silicon around specific workloads, software stacks, memory systems and deployment economics. A hyperscaler may accept the high non-recurring engineering cost because sufficiently large deployment volumes can improve performance per watt, reduce dependence on a single merchant accelerator vendor and give the operator greater control over future hardware-software co-design.

But a custom accelerator is not merely an arithmetic core. It requires high-speed interfaces, memory controllers, SerDes, packaging, physical design, verification and a reliable path to advanced-node manufacturing. The difficulty of converting a logical architecture into a manufacturable device creates a role for companies with reusable IP, physical-design experience and deep foundry relationships.

Marvell's strategic value is broader than "ASIC design services"

Calling Marvell an ASIC vendor can obscure the system-level nature of the work. A custom XPU project can draw on Marvell's interface IP, SerDes, security, networking, packaging and advanced-node implementation capabilities. It can also place Marvell close enough to the customer's architecture to identify adjacent needs in networking, memory, storage and interconnect.

This is important because the commercial value of a hyperscaler relationship does not have to end at the main accelerator. If Marvell can supply products that attach to the XPU ecosystem, the company can participate even when the central compute die is designed by another partner.

Custom silicon economics: NRE, reusable IP and volume risk

A custom XPU program has two broad economic phases. The first is development: architecture, RTL integration, verification, physical design, interface IP, package planning and tape-out. Customers may pay non-recurring engineering fees, but the strategic payoff for a supplier comes if the device enters high-volume production. The second phase is therefore a manufacturing and product-revenue phase in which the semiconductor partner's economics depend on repeated delivery at the required yield, cost and schedule.

This structure explains why reusable IP matters. A hyperscaler wants differentiation in the compute blocks that create workload advantage, but it does not necessarily want to reinvent every SerDes, PCIe controller, memory interface, security block or high-speed PHY for every generation. A merchant supplier with validated interface IP can reuse years of engineering across multiple customer programs. The customer receives shorter time to market; the supplier spreads R&D over more designs.

It also explains why custom silicon is not automatically a superior business to merchant silicon. Hyperscalers have enormous bargaining power, programs can be concentrated in a small number of customers, and revenue can move sharply if a tape-out or deployment schedule changes. Marvell's broader connectivity portfolio is therefore strategically valuable as a counterweight: the company can participate in the same AI buildout through standardized optical, switching, CXL and storage products even when it does not own the main custom accelerator.

The strategic shift is from winning a chip to winning positions around a system

In a system composed of thousands of accelerators, the main XPU is only one component class. The surrounding infrastructure may include NICs, memory controllers, CXL switches, PCIe retimers, Ethernet switches, DSPs, optical modules and storage controllers. Some products are standardized; others can be customized for the operator's architecture.

This leads to a different way to interpret Marvell's custom business. The objective is not necessarily to replace every competing custom-silicon provider. It is to increase the number of sockets and interconnect positions around a growing AI system.

The Google Agreement: From a Custom Chip Project to the TPU Ecosystem

The scope of the 2026 agreement is the important part

On July 29, 2026, Marvell and Google entered into an expanded commercial agreement for custom semiconductor products. Marvell's August 19 Form 8-K described a range of programs that "attach to the TPU ecosystem," including AI inference accelerators, storage controllers, network interface controllers, memory interface controllers and near-memory compute.

That list is unusually revealing because it crosses several functional boundaries. Compute is present, but so are network, storage and memory. The agreement therefore supports a broader interpretation of Marvell's position: the company is not only participating in a central accelerator project; the disclosed scope also includes infrastructure silicon around Google's TPU architecture.

The filing is unusually valuable because it replaces market inference with a legal description of the commercial scope. The listed products are the kinds of components normally discussed separately by semiconductor analysts, yet Google and Marvell grouped them under one expanded relationship attaching to the TPU ecosystem. That is direct evidence that hyperscaler custom-silicon procurement can extend across an architectural family of chips rather than a single hero device.

The warrant exhibit adds another detail: it defines qualifying products in a way that gives Google a sale-control right over the relevant custom products and refers to a product called Kestrel in the warrant mechanics. The public filing does not provide enough information to infer Kestrel's full technical role, so it does not constitute evidence of a specific accelerator roadmap. What the filing does establish is that the commercial relationship is specific enough to define qualifying custom products, revenue recognition and vesting events over a multi-year period.

The warrant links potential Google ownership to future product purchases

In connection with the expanded collaboration, Marvell issued Google a warrant to purchase up to about 59.0 million Marvell common shares at an exercise price of $206.58 per share. The structure is often summarized in headlines as a potential stake of roughly 7%, but that shorthand can be misleading. Google did not simply receive an immediate 7% ownership position.

About 1.36 million warrant shares are time-based. The remaining shares vest according to qualifying purchases from the third quarter of fiscal 2027 through fiscal 2033. The agreement divides the performance-based portion into 240 equal tranches, with one tranche vesting for each $500 million of Custom Products revenue. Multiplying those thresholds produces a theoretical $120 billion of qualifying cumulative Custom Products revenue for all 240 tranches to vest.

The structural meaning is more important than the headline value of the warrant. The arrangement creates a long-duration link between Google's purchasing volume and its potential equity participation in Marvell. It therefore aligns the customer's incentive with the commercial expansion of Marvell's custom silicon inside the TPU ecosystem. It does not constitute guaranteed future revenue; purchases are discretionary and the warrant remains conditional.

The arithmetic is large, but the distinction between capacity and commitment is essential

At issuance, Marvell disclosed about 876.9 million common shares outstanding. The maximum warrant shares were therefore equivalent to about 6.7% of that pre-warrant share count. The exercise price is $206.58 per share, so a full cash exercise at the stated price would involve more than $12 billion of exercise value before any adjustments. The warrant also permits cashless exercise under specified conditions, meaning the eventual cash and dilution effects cannot be inferred simply by multiplying shares by exercise price.

The structure is nevertheless notable as an indicator of potential duration. Performance vesting runs from Marvell's third quarter of fiscal 2027 through the end of fiscal 2033, and the warrant expires in August 2033. A multi-year framework is more consistent with a long-duration infrastructure relationship than with a one-generation component win, although it does not establish future purchase volume. It creates an incentive for Marvell to keep expanding the set of qualifying products and for Google to benefit if those purchases coincide with Marvell equity appreciation.

Why this matters for the data-movement thesis

The Google agreement is a real-world test of the idea that AI infrastructure is expanding beyond the processor. If the partnership covered only a single inference ASIC, the thesis would remain narrower. Instead, it explicitly includes the controllers and interfaces that connect compute to network, memory and storage.

That is precisely the direction implied by the broader Marvell portfolio: AI infrastructure is becoming a system of tightly coupled resources, and the commercial opportunity grows wherever data has to cross a boundary between those resources.

XPU Attach: The Semiconductor Market Around the Main Accelerator

Defining the concept

"XPU Attach" is useful shorthand for the silicon surrounding a main processor or accelerator. The exact products differ by architecture, but the category can include custom NICs, memory controllers, CXL devices, storage controllers, security or offload engines and other interface components. The concept matters because it changes the unit of analysis from one expensive accelerator to an entire rack-level system.

The 1-to-many multiplier

A single XPU can drive demand for multiple adjacent components and multiple high-speed links. A rack with many XPUs therefore creates a multiplier effect: compute growth can translate into growth in network interfaces, retimers, switch capacity, optical ports and memory connectivity. The precise ratio varies by design and is not a universal constant. The structural point is that the attach opportunity can expand faster than the count of primary compute devices.

Attach is where custom design can meet merchant infrastructure

XPU attach is strategically interesting because it blurs the boundary between fully custom chips and standardized infrastructure. A hyperscaler may want a custom NIC tailored to its topology while still using standard Ethernet on the wire. It may want a CXL controller optimized for a proprietary memory hierarchy while relying on an industry-standard CXL protocol. It may use a custom storage offload engine while connecting to commodity NAND and SSDs.

This is a favorable position for a company with both custom-silicon and merchant-interface capabilities. The custom team understands the customer's accelerator and software requirements; the merchant team contributes proven PHYs, controllers, retimers and networking IP. The theoretical synergy is not simply cross-selling. It is the ability to design the attach silicon with knowledge of the interfaces and physical channels on both sides.

The Google agreement provides a concrete example because it explicitly includes network interface controllers, memory interface controllers, storage controllers and near-memory compute around the TPU ecosystem. Those categories correspond almost exactly to the attach thesis: the accelerator is only one element of a larger data path, and the surrounding silicon can become a meaningful share of the system semiconductor content.

That breadth extends Marvell's participation beyond the central compute die without eliminating customer concentration risk. Rather than restating the same strategic implication here, the system-level effect is summarized later in Marvell's full AI data-movement stack.

The Memory Wall: Data Movement Is Not Only a Networking Problem

AI can stall because memory is too small, too distant or too slow

The phrase "data movement" often makes people think first about Ethernet and fiber. But memory traffic can be just as important. Large inference workloads depend on model parameters, key-value cache, retrieval data and application state. If those resources cannot be supplied with sufficient capacity and bandwidth, the accelerator may spend more time waiting.

Marvell has explicitly framed modern AI inference as a memory-infrastructure challenge. Its 2026 portfolio announcements connect AI storage, rack-level memory expansion and pooling, and pod-level optical shared memory. This is significant because it places storage and memory architecture inside the same broader thesis as networking: both are mechanisms for moving data to where compute can use it.

CXL turns memory into a more flexible infrastructure resource

Compute Express Link is designed to provide coherent connectivity between processors and devices over a PCIe physical foundation. In data-center architectures, CXL can support memory expansion and pooling, allowing capacity to be provisioned more flexibly than in a purely local-memory model.

Marvell's Structera portfolio includes memory-expansion controllers, near-memory acceleration and CXL switching. The Structera S family is intended to make disaggregated memory available at rack scale, while other Structera devices address expansion and near-memory functions. These products target a simple economic problem: expensive compute is poorly utilized when memory capacity and bandwidth cannot keep up.

Marvell is extending the memory hierarchy from SSD to pooled DRAM to optical shared memory

Marvell's August 2026 memory announcement makes the architecture more concrete. At the server level, the Bravera SC6 PCIe 6.0 SSD controller is designed to help inference systems move portions of KV cache from scarce high-bandwidth memory to flash storage. At the rack level, Structera X and Structera S are intended to expand and pool DRAM over CXL. At the pod level, Photonic Fabric is being positioned as an optical shared-memory tier spanning multiple racks.

This tiering matters because AI memory does not have one uniform value. Parameters or cache needed immediately are generally most valuable in the fastest local memory. Warm data can live farther away if the interconnect keeps latency and bandwidth within acceptable limits. Colder data can sit on SSD. The economic challenge is to place each byte in the cheapest memory tier that still meets performance requirements, then move it efficiently when the workload changes.

Marvell says its Photonic Fabric memory architecture is designed to extend a shared tier across multiple XPUs and racks over distances up to 50 meters, with up to 32 TB of warm KV-cache offload. The company also claims the architecture can enable up to 2–3 times higher token throughput within existing data-center footprint and power envelopes. These are vendor claims and remain subject to real-world system validation, but they show the direction of the product strategy: optics is being used not only to network servers, but to reshape the memory hierarchy itself.

The Bravera SC6, meanwhile, moves to PCIe 6.0 and is designed to support NAND from multiple suppliers. That may look distant from photonics, yet both products attack the same economic problem from different latency tiers: prevent expensive accelerators from stalling because the required data is trapped in the wrong place.

Memory infrastructure expands Marvell's definition of connectivity

This is why "AI communications" is too narrow a description of the company's direction. A NIC moves packets. A PAM4 DSP moves signals across optical links. A CXL device moves and exposes memory resources. A storage controller moves data between NAND and the system. All are different physical or protocol layers of the same underlying activity: making data available to computation.

XConn and Electrical Scale-Up: Connecting More Accelerators Before Optics Takes Over

Scale-up and scale-out solve different problems

AI networks are often described as if all interconnect were the same. It is useful to separate two domains. Scale-up connects accelerators inside a tightly coupled compute domain where very low latency, high bandwidth and memory-like semantics are valuable. Scale-out connects larger numbers of servers, racks or pods through networking fabrics such as Ethernet.

Both domains are expanding. As scale-up domains become larger, they extend across more boards and racks. As clusters become larger, scale-out networks carry more aggregate traffic. This creates demand for different switch types, protocols, retimers and optical technologies.

XConn adds PCIe and CXL switching and strengthens the UALink roadmap

Marvell completed its acquisition of XConn Technologies on February 10, 2026. XConn brought advanced PCIe and CXL switching silicon. Marvell also said the acquisition strengthens its engineering resources for UALink scale-up switching.

UALink is an open accelerator interconnect designed for high-bandwidth, low-latency communication inside AI computing pods. Marvell's decision to add XConn therefore fits directly into the transition toward larger multi-rack scale-up domains and gives the company a deeper engineering base for open scale-up switching.

XConn adds a measurable commercialization path, not only protocol IP

Marvell provided a financial ramp when the acquisition closed. The company expected initial XConn revenue in the third quarter of fiscal 2027, a roughly $50 million annualized run rate by the fourth quarter of fiscal 2027, and approximately $100 million of fiscal 2028 revenue. Those numbers are small relative to Marvell's overall data-center business, but they are useful because they show that XConn is intended to become a shipping product line while its engineering team also contributes to the longer-term UALink roadmap.

The acquisition also illustrates the cost of building a broader stack. Marvell disclosed that the transaction reduced cash by about $325 million, added roughly $25 million of annual non-GAAP operating expenses and increased diluted weighted-average shares by about 2.7 million. A connectivity strategy assembled through acquisitions therefore creates integration and dilution costs before the new markets reach scale.

Strategically, XConn gives Marvell a bridge between point-to-point interfaces and fabric-level resource composition. Retimers help preserve signal integrity across difficult electrical channels; switches determine which devices and memory resources can communicate with which other devices. Moving from retimers into high-radix switching therefore expands the company's role from preserving a link to shaping the topology of the system.

Electrical connectivity remains essential even in an optical future

The growth of optical interconnect does not make electrical fabrics disappear. PCIe, CXL, UALink and SerDes remain essential at many distances and inside many packages, boards and racks. The transition is better understood as a changing boundary: as electrical reach becomes more expensive in power and signal integrity, optical links can move closer to the compute.

This makes XConn and Celestial AI complementary in strategic direction even though they operate in different technology domains. One strengthens the electrical scale-up stack; the other is aimed at moving more of that scale-up traffic into optics.

Why High-Speed Electrical Links Eventually Meet a Physical Wall

SerDes is the basic translator between parallel computation and serial links

Inside a chip, data can move across wide parallel buses over very short distances. Crossing a chip boundary is different. Pin count, board area, skew and interference make it impractical to preserve very wide parallel signaling over distance. Serializer/deserializer technology solves this by converting parallel data into high-speed serial streams for transmission and reconstructing the data at the receiving side.

At high speeds, the receiver recovers a signal that has been degraded by attenuation, reflections, crosstalk and noise. Equalization, clock recovery and analog design therefore become critical. This is one reason high-speed SerDes IP is difficult to commoditize: the interface may be logically standardized, but reliable operation at the physical limit requires deep mixed-signal engineering.

PAM4 increases bandwidth by making the signal more fragile

Pulse-amplitude modulation with four levels, or PAM4, carries two bits per symbol by encoding four amplitude levels rather than the two levels used by NRZ signaling. The benefit is higher data throughput per channel. The cost is smaller separation between signal levels and therefore greater sensitivity to noise and distortion.

DSPs can compensate for channel impairments through equalization, clock recovery and error-management techniques. In optical modules, this processing becomes the digital intelligence that makes very high-speed links practical. Marvell's Inphi-derived PAM4 portfolio therefore sits at a crucial conversion point between electrical signals from switches or accelerators and optical transport across fiber.

Power per bit becomes a system constraint

The issue is not simply whether a link can function. Commercially useful links also operate within acceptable power budgets. In a large AI cluster, thousands of ports and lanes operate simultaneously. If the energy required to move each bit rises too quickly with speed or distance, networking and interconnect consume a growing share of the rack's power and cooling budget.

This is why the industry increasingly evaluates interconnect by a combination of bandwidth, latency, reach and energy per bit. The transition toward optics is not driven by one parameter alone. It emerges from the combined physical cost of moving more information across longer distances at higher speed.

Marvell's Optical Stack: From 1.6T Modules to Data-Center Interconnect

Optics exists at multiple distance scales

"Optical networking" is not one market. Different technologies serve different reach, bandwidth and cost requirements. Shorter links connect servers and switches inside a data center. Longer coherent links connect buildings, campuses or data centers. As AI systems scale, demand can rise at multiple distances simultaneously.

Marvell's 2026 OFC portfolio illustrates that breadth. The company showcased 1.6T PAM4 optical DSP technology for AI scale-out, transmit-retimed optics, CXL memory products, Ethernet switch silicon, Photonic Fabric scale-up technology and 800G ZR/ZR+ coherent optics for data-center interconnect.

A distance ladder helps explain why Marvell keeps adding optical products

One way to organize the optical portfolio is by reach. In an OFC 2026 demonstration with Lumentum, Marvell described Ara-powered 1.6T modules for links ranging roughly from 5 meters to 2 kilometers, Aquila coherent-lite technology for campus-class links of roughly 2 to 20 kilometers, and COLORZ ZR/ZR+ modules for links extending from about 10 kilometers toward 1,000 kilometers. Its newer coherent products extend that envelope further depending on line rate.

The engineering problem changes as reach increases. Short-reach PAM4 links prioritize power, density and low cost per port. Campus links need more sophisticated coherent processing while preserving pluggable economics. Metro and regional DCI require coherent modulation, forward-error correction, optical compatibility and security features such as MACsec. A company that can move between these domains can follow AI traffic as it leaves the rack and spreads across a campus or region.

Marvell's March 2026 optical announcements show how aggressively it is pushing the speed ladder. The Ara family uses 200G-per-lane electrical and optical interfaces to build 1.6T modules, and the company said Ara was already shipping in mass volume. For longer-reach coherent links, Marvell introduced COLORZ 1600 with its 2nm Electra coherent DSP and described support for 1.6T connectivity across campus, metro and regional distances up to about 1,000 kilometers under specified modes.

The Inphi heritage now serves AI scale-out

Inphi's legacy technologies were originally important to cloud and telecom data movement. AI changed the intensity of the demand. Scale-out networks now need to connect enormous numbers of accelerators with rapidly increasing port speeds. Moving from 800G toward 1.6T increases the value of highly integrated DSPs, analog front ends and silicon-photonics integration that can reduce power and improve signal integrity.

This creates a recurring revenue logic distinct from the central custom XPU. Every new generation of AI scale-out bandwidth can require new optical components even when the underlying accelerator architecture changes.

Coherent optics extends the same data-movement thesis beyond the rack

As AI deployments spread across buildings and campuses, traffic travels farther than ordinary short-reach optics can efficiently serve. Coherent DSP technology enables high-capacity optical transport over longer distances. Products such as ZR and ZR+ pluggable optics therefore connect the AI infrastructure story to data-center interconnect.

At this point, Marvell's addressable path is no longer just "chip to chip." It can extend from interfaces inside servers, through rack and pod fabrics, to optical links connecting data-center domains.

Celestial AI: Moving Optics into the Scale-Up Domain

Why acquire another optical technology company after Inphi?

Inphi solved one class of high-speed data movement: turning electrical data into optical transport for high-speed networking and data-center interconnect. Celestial AI targets a different problem. Its Photonic Fabric technology is designed for high-bandwidth, low-latency optical connectivity inside large AI scale-up systems.

Marvell completed the acquisition on February 2, 2026 and described it as an expansion into the emerging scale-up interconnect market. The strategic premise is that electrical connectivity becomes increasingly difficult as scale-up systems extend across larger physical domains. If optics can move closer to the XPU and memory fabric, the system may be able to expand bandwidth and reach without paying the same electrical power and signal-integrity penalties.

The transaction also carried a quantified commercial expectation. Marvell said it expected initial Celestial AI revenue in the second half of fiscal 2028, ramping to a $500 million annualized run rate in the fourth quarter of fiscal 2028 and then doubling to a $1 billion annualized run rate by the fourth quarter of fiscal 2029. Those figures are management forecasts, not realized revenue, but they show that Marvell did not purchase Celestial AI as a distant research project. It expects the technology to become a material business within several years.

The commitment is material as well. Marvell said the acquisition reduced its cash balance by approximately $1 billion and added around $50 million of annual non-GAAP operating expense. Those costs matter for a balanced interpretation: Photonic Fabric expands the addressable infrastructure opportunity, but Marvell incurs integration, product-development and commercialization costs well before any expected revenue ramp arrives.

Photonic Fabric Is Distinct from a Single CPO Category

Several optical architectures are evolving simultaneously: pluggable optics, linear pluggable optics, co-packaged optics, optical I/O and optical fabrics. They differ in where the optical conversion occurs, how tightly it is integrated with compute or switching silicon, what protocols they carry and which distances they serve.

Celestial AI's Photonic Fabric is best understood as an attempt to use optics as part of the scale-up fabric itself. Marvell has described the technology as supporting high-bandwidth, low-latency, power-efficient connectivity across large AI deployments and enabling multi-rack optical scale-up. That makes it strategically different from merely improving the transceiver on a conventional scale-out Ethernet link.

The opportunity is large because the risk is large

The same factor that makes Photonic Fabric strategically interesting also makes it uncertain. Scale-up interconnect is deeply coupled to system architecture. Successful deployment depends on standards, software, packaging, reliability, yield, thermal behavior and hyperscaler qualification. A technology can demonstrate strong laboratory performance yet still struggle to achieve the cost and reliability required for enormous production volumes.

For that reason, Celestial AI remains an emerging architectural option rather than evidence of a future leading standard. The acquisition increases Marvell's exposure to optical scale-up; it does not establish displacement of every electrical approach or complete market capture by Marvell.

NVIDIA: Evidence That Marvell Can Participate Inside a Competing Compute Ecosystem

A $2 billion strategic investment and NVLink Fusion collaboration

On March 31, 2026, NVIDIA and Marvell announced a strategic partnership around NVIDIA NVLink Fusion. Marvell is expected to provide custom XPUs and NVLink Fusion-compatible scale-up networking, while the companies also plan to collaborate on silicon photonics. NVIDIA invested $2 billion in Marvell through convertible preferred stock.

The relationship is important because NVIDIA and Google represent very different AI compute ecosystems. Google is expanding around its TPU architecture. NVIDIA is expanding an ecosystem centered on NVIDIA compute, networking and NVLink. Marvell has found a role in both.

The implication is not literal architecture neutrality—Marvell remains subject to each ecosystem's interfaces, qualification process and economics—but the partnership is evidence that its connectivity role can exist inside a platform it does not control. The broader cross-architecture thesis is stated once in the stack synthesis below.

NVIDIA also shows where Marvell is complementary rather than controlling the platform

The NVIDIA partnership does not imply that NVIDIA is outsourcing its infrastructure stack to Marvell. NVIDIA remains a formidable supplier of ConnectX NICs, BlueField DPUs, Spectrum-X Ethernet switches, NVLink interconnect and rack-scale systems. The announced division of labor explicitly keeps many of those technologies inside NVIDIA's own platform while Marvell contributes custom XPUs, NVLink Fusion-compatible scale-up networking and silicon-photonics collaboration.

That distinction reinforces the central argument. Marvell's opportunity can exist inside a platform controlled by another company because no single AI rack is composed of one semiconductor. The relevant question is whether Marvell can secure high-value interfaces and custom devices at the boundaries where the platform owner benefits from external specialization or customer choice.

NVIDIA's $2 billion investment adds a financial alignment mechanism that is different from Google's performance-based warrant but directionally similar: a major AI platform owner has chosen not only to buy or integrate technology, but also to hold an economic interest tied to the relationship. The two transactions cannot be combined into a guaranteed revenue forecast, yet together they demonstrate that Marvell is being positioned as a strategic supplier to multiple architectural camps.

Reality Check: The Q2 FY2027 Results Show the Thesis Entering the Income Statement

Data center already defines the revenue mix

Marvell reported its second quarter of fiscal 2027 on August 27, 2026. Net revenue reached a record approximately $2.74 billion, up 37% year over year. Data-center revenue reached approximately $2.17 billion, up 46% year over year and 18% sequentially.

Most important for the structural argument, data center represented 79% of total revenue, compared with 76% in the preceding quarter and 74% a year earlier. In other words, Marvell is no longer merely a diversified semiconductor company with an attractive AI segment. Its revenue composition has already shifted decisively toward data-center infrastructure.

Management explicitly identified both Connectivity and Custom as growth drivers

CEO Matt Murphy said the quarter reflected strong demand across the Data Center portfolio and that AI-related bookings remained exceptionally robust. More revealingly, he described "broad-based strength" that included strong demand in Connectivity and a significant acceleration in the Custom business beginning in the second half of fiscal 2027.

That language matters because it matches the architecture described in this article. If Marvell's AI growth came only from one or two custom accelerators, the data-movement thesis would be weaker. The reported strength in both custom silicon and connectivity suggests that compute and the infrastructure around compute are scaling together.

The near-term financial signal is acceleration, not completion

For the third quarter of fiscal 2027, Marvell guided to approximately $3.15 billion of revenue, plus or minus 5%. It also said it was again raising its revenue outlook for both fiscal 2027 and fiscal 2028, while reserving a more detailed long-term discussion for its October 6, 2026 Investor Day.

The updated multi-year outlook makes the acceleration measurable

On the earnings call, management placed more numbers around the longer-term trajectory. Marvell now expects approximately $12 billion of fiscal 2027 revenue, or roughly 45% year-over-year growth, compared with a prior outlook of about $11.5 billion. It expects Data Center revenue to grow about 60% in fiscal 2027, up from a previous expectation near 50%.

For fiscal 2028, management raised its revenue outlook to approximately $18 billion, $1.5 billion above the $16.5 billion outlook issued only one quarter earlier. That would imply roughly 50% year-over-year company growth. Management also said it expected Data Center revenue to grow more than 60% in fiscal 2028 and the custom business to more than double.

These figures are forward-looking rather than reported results. They nevertheless provide a scale test for the thesis. A company that generated approximately $2.74 billion in the latest quarter is telling the market that annual revenue could approach $18 billion within roughly a year and a half, with data center growing faster than the company. If that trajectory is achieved, connectivity and custom silicon are no longer peripheral AI exposures; they are the main economic engine of Marvell.

Margins reveal the cost of the growth mix

The quarter also shows that rapid revenue growth does not imply effortless profitability. Q2 FY2027 GAAP gross margin was 53.1% and non-GAAP gross margin was 58.9%. For Q3, Marvell guided to a non-GAAP gross margin range of 57.5% to 58.5%, slightly below the Q2 result even as revenue is expected to rise sharply.

That pattern is consistent with a company whose mix is shifting toward large custom programs and rapidly scaling data-center products. Custom silicon can produce very large revenue, but hyperscalers possess strong negotiating leverage and the economics differ from proprietary merchant products such as DSPs. Marvell therefore needs growth in higher-value connectivity, optics and memory infrastructure to help preserve the financial quality of the overall portfolio.

Cash generation remains meaningful, while the same cash base also funds expansion. Q2 produced approximately $606 million of operating cash flow. At the same time, Marvell has spent cash on Celestial AI and XConn, is investing in advanced-node products, and its expansion depends on access to manufacturing capacity for a much larger revenue base. The financial story is therefore not simply higher sales; it is the conversion of a historically broader chip company into a more capital-committed AI infrastructure supplier.

Forward guidance is not evidence in the same way realized revenue is. It can change. The more reliable reality check is the current mix: 79% data-center exposure, 46% year-over-year data-center growth and management identification of Connectivity plus Custom as simultaneous growth engines.

The strongest evidence is now revenue composition

Marvell's product roadmap can always be interpreted as aspiration. Acquisitions can be interpreted as strategic intent. Customer agreements can indicate future opportunity. Financial results are different: they reveal which markets are already paying the company.

The transformation becomes clearer when the latest quarter is placed beside the previous three fiscal years. Data-center revenue rose from approximately $2.22 billion, or 40% of company revenue, in FY2024 to approximately $4.16 billion, or 72%, in FY2025 and approximately $6.10 billion, or 74%, in FY2026. Q2 FY2027 then reached approximately $2.17 billion in a single quarter, or 79% of quarterly revenue. The annual and quarterly figures are not directly comparable periods, but together they show that data center moved from one major end market to the primary economic identity of the company.

Period	Data-center revenue	Share of total revenue	What changed
FY2024	$2.22B	40%	Data center was important, but Marvell still had a much broader revenue mix.
FY2025	$4.16B	72%	Data center became the clear majority of company revenue.
FY2026	$6.10B	74%	AI-related custom products and electro-optics were major contributors to continued expansion.
Q2 FY2027	$2.17B	79%	The latest quarterly mix shows the transformation continuing rather than reversing.

The strongest current evidence for Marvell's transformation is therefore no longer only its product roadmap. It is the composition of its revenue. The system-level portfolio and the income statement are beginning to point in the same direction.

Q2 FY2027 metric	Reported result	Structural interpretation
Total revenue	$2.74B, +37% YoY	Company-level growth is increasingly being driven by AI and data-center infrastructure.
Data-center revenue	$2.17B, +46% YoY, +18% QoQ	Data center is growing faster than the company as a whole.
Data-center mix	79% of revenue	The transformation is already visible in the business mix, not only in future roadmaps.
Management commentary	Connectivity strength + Custom acceleration	Supports a broader thesis than custom ASIC alone.
Q3 FY2027 guide	~$3.15B ±5%	Near-term demand remains strong, though guidance is forward-looking and uncertain.
Q2 non-GAAP gross margin	58.9%	Shows that rapid custom/data-center growth remains subject to product-mix economics.
Operating cash flow	~$606M	Provides internal funding capacity while Marvell absorbs acquisition and scaling costs.
FY2027 outlook	~$12B revenue; ~45% YoY	Management expects the current acceleration to persist through the fiscal year.
FY2028 outlook	~$18B revenue; ~50% YoY	Would make AI/data-center infrastructure the overwhelming determinant of company scale if achieved.

Putting the Pieces Together: Marvell's AI Data Movement Stack

The individual product lines become easier to understand when arranged by the resource boundary they cross.

Infrastructure domain	Representative Marvell position	What data is being moved
Custom compute	Custom XPU / AI accelerator development	Workload execution inside hyperscaler-specific architectures
XPU attach	Custom NICs, controllers, offload silicon	Traffic between the XPU and network, storage or supporting devices
Memory	Structera CXL expansion, pooling and near-memory acceleration	Data between compute and disaggregated or expanded memory
Electrical scale-up	PCIe, CXL and UALink-related switching; retimers	Low-latency accelerator and memory traffic within scale-up domains
Scale-out networking	Ethernet switching and high-speed interfaces	Traffic across servers, racks and pods
Optical interconnect	PAM4 DSPs and 800G/1.6T optical technologies	High-bandwidth traffic across fiber within data centers
Optical scale-up	Celestial AI Photonic Fabric	High-bandwidth, low-latency traffic deeper inside multi-rack scale-up systems
Data-center interconnect	Coherent DSP and ZR/ZR+ optical technologies	Traffic across buildings, campuses and data-center domains

The table reveals the common denominator. These businesses are not identical, and they face different competitors. But they all become more valuable when AI systems need to move more information across more boundaries.

The stack can also be read as a distance map

Another way to view the same portfolio is to ask how far the data travels. Inside and immediately around a processor, high-speed SerDes, memory interfaces and custom controllers dominate. Across a board and rack, PCIe, CXL, retimers and scale-up switches become important. Across racks, Ethernet switches and PAM4 optics carry the load. Across a campus or region, coherent DSPs and ZR/ZR+ optics take over. Photonic Fabric attempts to break this traditional distance segmentation by using optical links earlier in the hierarchy.

This distance map helps explain why apparently adjacent products can have very different competitive dynamics. A company may be excellent at switch silicon but lack coherent optics. Another may produce lasers but not DSPs. A third may own an accelerator fabric but not merchant CXL. Marvell's strategic bet is that having engineering depth across several transitions allows it to participate when customers redesign where electrical signaling ends and optical signaling begins.

The most valuable control point may move over time

AI infrastructure remains early enough in its development that the binding bottleneck can migrate. During one generation it may be HBM capacity; during another, scale-up bandwidth; later, optical power or DCI capacity. A narrow supplier can grow rapidly while its particular bottleneck is acute and then slow when architecture moves elsewhere. Marvell's portfolio is an attempt to reduce that dependence by holding positions across several possible future constraints.

This does not imply that every product grows at the same time. Some layers can cannibalize others. Better CXL memory utilization could reduce the need for some local DRAM. Optical scale-up could eventually replace some long electrical links. Transmit-retimed optics can reduce DSP functionality relative to fully retimed modules in certain use cases. The strategic advantage is therefore not that all products stack arithmetically, but that Marvell can remain relevant as the system chooses different solutions to the same data-movement problem.

One strategic consequence follows from the stack as a whole: every successful compute architecture creates an interconnect bill. NVIDIA GPUs, Google TPUs, Amazon Trainium and Microsoft Maia can compete for workload share while all increasing demand for memory connectivity, switching and optics. The 2026 Google and NVIDIA relationships provide two different real-world examples of Marvell fitting into architectures controlled by larger platform owners. That does not make the company architecture-neutral or immune to vertical integration; it means its opportunity is not limited to owning the central compute die.

What Marvell Does Not Control: The Physical Supply Chain Still Matters

Portfolio breadth can create the impression that Marvell is vertically integrating the entire AI data center. It is not. Marvell is a fabless semiconductor company. Its August 2026 Form 10-Q states that it does not own manufacturing, assembly or packaging facilities and has only very limited in-house testing capability. The company's core leverage therefore comes from architecture, IP, custom design, interfaces, signal processing and customer co-development—not from owning the factories that physically produce the chips.

This distinction is structurally important because Marvell's most advanced products still depend on external manufacturing capacity. The same filing identifies TSMC as the sole-source foundry for all of Marvell's advanced process-node wafers and notes that availability of advanced-node wafer capacity is constrained while product demand is strong. Assembly, testing and packaging are also outsourced to third parties concentrated across several Asian and North American locations.

Marvell therefore sits inside a larger dependency chain. A custom XPU or optical DSP can be architecturally valuable and commercially sold, but it still requires advanced lithography, foundry execution, substrates, packaging and test before it can become deployed infrastructure. That upstream manufacturing concentration is why the company's data-movement role complements rather than replaces the semiconductor-production bottlenecks examined in How Lithography Consolidated Around ASML.

The boundary is useful for defining Marvell's actual structural position. The company does not control leading-edge wafer manufacturing, HBM production or complete AI rack systems. It is attempting to control and co-design valuable interfaces between resources. If that distinction is kept clear, Marvell's breadth looks less like full vertical integration and more like a horizontal layer of connectivity and custom infrastructure sitting on top of a manufacturing ecosystem it does not own.

The Moat: Where Marvell Is Difficult to Replace

High-speed analog and mixed-signal engineering

SerDes, PAM4 DSPs, coherent DSPs and retimers operate close to physical signal limits. Their performance depends on analog design, equalization, clock recovery, power management and manufacturing behavior that are difficult to reproduce simply by reading a protocol specification. The Inphi acquisition deepened Marvell's institutional knowledge in this area.

Hyperscaler co-development

Custom silicon is relational as well as technical. Large programs require years of architecture work, verification, tape-out, packaging, software coordination and volume ramp. Once a supplier is embedded in a program and has demonstrated execution, switching is possible but costly. The Google warrant is an unusually visible example of a relationship being structured for long-duration commercial expansion.

Breadth across electrical and optical interconnect

Marvell can combine custom compute, Ethernet, PCIe/CXL, SerDes, DSP and optical technologies inside one portfolio. Breadth is not the same as dominance, but it can create design advantages when customers want to optimize across device boundaries rather than purchase isolated components.

The value of that breadth is optionality across where the bottleneck migrates, a point already mapped in the data-movement stack. It does not imply that Marvell wins every layer; it means the company has more than one technical path through which AI infrastructure growth can become semiconductor demand.

Leading-edge design and qualification knowledge compound over generations

Advanced connectivity is increasingly a leading-edge semiconductor problem. Marvell's 1.6T Ara optical DSP is built on 3nm technology, while newer coherent DSP roadmaps move toward 2nm. Advanced nodes can lower power and increase integration, which is particularly valuable for dense optical and AI systems where every watt of communication overhead competes with compute for the same facility power envelope.

The defensible capability is not ownership of the fab; as noted above, Marvell depends on external manufacturing. The institutional advantage comes from repeatedly taking high-speed products through architecture, physical design, foundry interfaces, packaging, firmware, test and hyperscaler qualification. Each successful generation produces engineering knowledge that is difficult to reproduce quickly even when the underlying protocol standard is public.

Competition: Marvell Is Broad, but It Does Not Own the Stack

A structural analysis benefits from separating portfolio breadth from any monopoly claim. Marvell competes against powerful companies at nearly every layer.

• NVIDIA controls a large integrated AI compute and networking ecosystem through GPUs, NVLink, ConnectX, BlueField and Spectrum-X.
• Astera Labs focuses on PCIe/CXL connectivity and memory fabric products.
• Credo competes in high-speed connectivity, DSP and active electrical cable technologies.
• Coherent and Lumentum participate in important optical component and module layers.
• Alchip, MediaTek and other custom-silicon providers can compete for hyperscaler ASIC design and implementation work.
• Hyperscalers themselves may vertically integrate more of the system over time.

Marvell's differentiated claim is therefore not that it controls AI data-center communication. A more defensible statement is that it is becoming one of the relatively few semiconductor companies with meaningful positions across several distinct data-movement domains.

The competitive map differs by layer. NVIDIA is vertically integrated around its own compute ecosystem. Astera Labs concentrates more heavily on PCIe/CXL connectivity and fabric-management opportunities. Credo is strong in high-speed electrical and optical connectivity, while Coherent and Lumentum own critical laser, optical component and module capabilities. No single comparison is exact because Marvell's strategic identity comes from the intersection of several domains rather than dominance of one layer.

Hyperscalers themselves are the most important wildcard. Google, Amazon, Microsoft and Meta already design more of their own silicon than they did five years ago. Over time they can internalize controllers, interfaces or networking functions that suppliers currently provide. Yet vertical integration also has limits: advanced mixed-signal PHYs, coherent optics, high-speed test, leading-edge physical design and standards interoperability require specialized teams. The supplier opportunity survives where outsourcing remains faster, lower risk or more economical than rebuilding every layer internally.

Open standards can cut both ways. Ethernet, CXL and UALink can reduce customer fear of proprietary lock-in and enlarge the market for merchant components, helping Marvell. But openness can also invite more competitors and compress margins. Proprietary ecosystems such as NVLink can create powerful performance advantages but concentrate control in one platform owner. Marvell's multi-ecosystem strategy is therefore a hedge against standards uncertainty, not an escape from competition.

Risks and Counterarguments

Customer concentration can rise as the company becomes more successful

Hyperscaler programs are large enough that a small number of customers can represent a significant share of revenue. Marvell's August 28, 2026 Form 10-Q makes that concentration measurable. One direct customer represented 16% of Q2 FY2027 revenue. One distributor represented 44% of quarterly revenue, while four customers represented 72% of gross accounts receivable at quarter end. For FY2026, Marvell's ten largest customers, including direct customers and distributors, represented 82% of total revenue.

The distributor figure does not represent a single hyperscaler end customer: a distributor can serve multiple end customers and geographies. Even with that distinction, the numbers show that Marvell's revenue and receivables are concentrated in a relatively small commercial network. Large design wins can accelerate growth quickly, but delayed ramps, customer insourcing, program changes or purchasing shifts can therefore have an outsized effect.

Custom silicon can grow revenue faster than gross margin

Custom products can carry different economics from merchant products. As the mix changes, strong top-line growth does not automatically translate into equal growth in gross margin. This matters because a company can become more strategically important while still facing pressure in product mix and profitability.

Photonic Fabric is still an execution problem, not only a physics argument

Optical scale-up can be compelling on bandwidth and power, but commercial production depends on satisfying cost, yield, reliability, packaging and software requirements. Celestial AI therefore represents both a significant opportunity and a significant commercialization challenge.

Standards remain fluid

NVLink, UALink, Ethernet, PCIe and CXL continue to evolve. Some functions may converge; others may remain proprietary. Supplier outcomes depend on supporting the standards customers actually adopt, not simply the technically elegant standards. Marvell's participation across several ecosystems reduces but does not eliminate this risk.

AI capital expenditure remains the upstream demand dependency

Data movement is structurally necessary, but demand is still tied to the pace of AI infrastructure deployment. If hyperscalers slow construction, delay clusters or improve utilization enough to reduce new hardware requirements, many layers of the interconnect chain would feel the effect simultaneously.

Foundry and packaging capacity remain upstream supply dependencies

Marvell's fabless model limits the amount of physical capacity it controls directly. The latest 10-Q states that TSMC is the sole-source foundry for all advanced process-node wafers and that advanced-node capacity is constrained. A successful design win can therefore fail to convert into the expected deployment schedule if wafers, substrates, packaging or test capacity are unavailable. This is a different risk from customer demand: the order may exist while the physical supply chain still limits execution.

Acquisition-led breadth can become organizational complexity

Inphi, Celestial AI and XConn contribute different engineering cultures, product cycles and customer relationships. Integrating them is not a purely financial exercise. Integration requires optical DSP teams, CXL switch teams, custom-silicon teams and photonics researchers to coordinate roadmaps without slowing the specialist execution that made the acquired companies valuable in the first place. Marvell's strategy benefits from breadth only if the organization can convert breadth into interoperable products and customer wins.

The Google framework does not erase customer concentration

A multi-year agreement with a hyperscaler can increase visibility while simultaneously making the supplier more dependent on that customer. The same $120 billion theoretical vesting ceiling that demonstrates the possible scale of the Google relationship also illustrates the concentration risk if a large portion of future custom revenue becomes tied to one ecosystem. Structural relevance and bargaining power are not the same thing: a supplier can be technically indispensable to a program while the hyperscaler remains the economically stronger party.

What Would Weaken This Thesis?

A structural thesis remains revisable. The argument in this article is not that every Marvell product succeeds, but that AI infrastructure is increasing the value of data movement and that Marvell has assembled a portfolio positioned across several of those boundaries. Future evidence would weaken or revise that conclusion if the following conditions emerge.

• Connectivity stops scaling with custom compute. If accelerator deployments continue to grow while Marvell's optical, switching, memory-interface and attach businesses fail to grow with them, the portfolio would be less integrated economically than it appears architecturally.
• Hyperscalers internalize more interface silicon. If major customers increasingly design their own NICs, CXL controllers, memory interfaces or scale-up switches and reduce reliance on merchant or co-developed silicon, Marvell's addressable role around the XPU would narrow.
• Photonic Fabric fails the production test. Celestial AI's commercialization depends on cost, yield, reliability, packaging and software integration at hyperscale volumes. A sustained commercialization delay would weaken the optical-scale-up portion of the roadmap even if the underlying physics remains attractive.
• Open scale-up and memory standards do not gain the expected deployment breadth. If CXL or UALink adoption remains limited, fragments into incompatible implementations, or is displaced by proprietary alternatives in the workloads that matter most, some of Marvell's electrical-fabric opportunities would shrink.
• Advanced-node manufacturing becomes a persistent limiter. If foundry, substrate or advanced-packaging constraints repeatedly delay ramps, design wins would not translate cleanly into deployed infrastructure or reported revenue.
• The Google relationship remains narrower than the contractual categories imply. The agreement allows a broad set of products around the TPU ecosystem, but future evidence would need to show that multiple categories become meaningful programs rather than remaining a legal framework with limited realized breadth.
• The revenue mix reverses materially. If data-center revenue falls back toward a minority of company revenue for structural rather than cyclical reasons, the evidence that Marvell has become an AI data-infrastructure company would need to be reconsidered.

These are not predictions of failure. They are checkpoints that make the thesis testable. The strongest future validation would be simultaneous evidence across product adoption, customer breadth, connectivity revenue, manufacturing execution and sustained data-center mix—not merely one large design win or one strong quarter.

Counterfactual Test: What Would Have to Change?

If Marvell's position across AI data movement were not structurally relevant over the next 5–15 years, continued accelerator deployment would need to occur without sustained growth in the memory interfaces, switching, high-speed electrical links, optical interconnects and adjacent custom silicon that connect those accelerators to the rest of the system.

Then several conditions would need to hold at the same time: hyperscalers would internalize a much larger share of interface silicon; open standards would fail to create durable merchant or co-development opportunities; optical scale-up would remain niche or materially delayed; and advanced-node or packaging constraints would repeatedly prevent design wins from becoming volume deployments.

But that combined alternative conflicts with current observable constraints. Marvell's data-center mix has risen to roughly 79% of quarterly revenue; the disclosed Google relationship spans compute, network, storage, memory and near-memory product categories; NVIDIA has made a strategic investment while collaborating on NVLink Fusion and silicon photonics; and Marvell's own filings show continuing dependence on TSMC and advanced packaging. These observations do not prove permanence. They narrow the set of plausible alternatives under current conditions.

Conclusion: Marvell's Structural Role in AI Data Infrastructure

The first stage of the AI infrastructure race was defined by a shortage of computation. The next stage is increasingly defined by the difficulty of turning many separate processors, memory devices, storage systems and data centers into one usable machine.

That transition changes what counts as strategic semiconductor infrastructure. Compute remains essential, but the useful output of compute depends on memory bandwidth, interface silicon, switching, SerDes, DSPs and optical fabrics. The larger the AI system becomes, the more important these connecting layers become.

Marvell's corporate evolution can be read through that lens. Cavium broadened infrastructure compute, Avera added the custom-ASIC execution layer, Inphi brought high-speed optical data movement, and Innovium added cloud switching. Structera expanded the company's role in memory infrastructure. XConn strengthened electrical scale-up through PCIe, CXL and UALink-related switching, while Celestial AI pushed the roadmap toward optical scale-up. Partnerships with NVIDIA and Google demonstrated relevance inside different compute ecosystems. Finally, the August 2026 financial results showed that the transformation is no longer only conceptual: 79% of quarterly revenue came from data center, and management identified both Connectivity and Custom as major sources of strength.

The chronology is unusually coherent. Marvell moved into infrastructure compute with Cavium in 2018, added deep custom-ASIC capability with Avera in 2019, and expanded into electro-optics and cloud switching through Inphi and Innovium in 2021. In 2025, it continued pruning non-core businesses such as automotive Ethernet. In February 2026, it completed Celestial AI and XConn, adding optical and electrical scale-up. In March 2026, the NVIDIA relationship tied Marvell into NVLink Fusion and silicon-photonics collaboration. In August 2026, Google disclosed an expanded TPU-ecosystem relationship covering accelerator, network, memory, storage and near-memory products. The same month, Marvell reported that data center had reached 79% of revenue.

None of those events alone establishes that Marvell becomes a leading AI infrastructure supplier. Together, however, they form a stronger pattern than a product announcement or a quarterly beat. Corporate strategy, acquisition history, product architecture, customer contracts and revenue composition are all moving in the same direction. That is the kind of multi-layer confirmation required before treating a company as structurally important in the K Robot Matrix.

The company is still exposed to customers that are far larger than itself, fast-changing standards and difficult manufacturing ramps. It does not own the foundries or packaging capacity on which its most advanced products depend, and several future growth engines remain roadmaps rather than realized businesses. The thesis is therefore not that Marvell has eliminated uncertainty. It is that the central structural question has become how much of the AI data-movement stack Marvell can occupy as systems scale, and whether those positions can survive customer insourcing, standards shifts and physical supply constraints.

The important question is therefore not whether Marvell becomes the leading AI processor company. It is whether the company can remain embedded in enough of the paths that connect processors to everything they need.

AI system scaling is constrained not only by how much computation can be deployed, but also by how efficiently that computation can exchange data. Marvell is positioning its portfolio around that second constraint.

Sources

• Marvell Technology — Second Quarter Fiscal 2027 Financial Results, August 27, 2026
• Marvell Technology — Form 10-Q for the Quarter Ended August 1, 2026: Customer Concentration, Manufacturing Dependencies and Current Business Mix
• Marvell Technology — 2026 Proxy Statement: Decade-Long Portfolio Transformation, Acquisitions and Divestitures
• Marvell Technology — Form 8-K: Expanded Google Custom Silicon Agreement and Warrant, August 19, 2026
• Marvell Technology — Google Warrant Exhibit 4.1: Vesting, Exercise and Qualifying Revenue Terms, August 19, 2026
• Marvell Technology — Completion of Celestial AI Acquisition and Expected Financial Impact, February 2, 2026
• Marvell Technology — Completion of XConn Technologies Acquisition and Expected Financial Impact, February 10, 2026
• Marvell Technology — AI Memory Infrastructure Portfolio, August 4, 2026
• Marvell Technology — End-to-End AI Data Center Connectivity Portfolio at OFC 2026
• Marvell Technology — Fiscal 2022 Form 10-K: Inphi and Innovium Acquisitions and Portfolio Integration